1. Field of the Invention
The present invention relates to a high level self-checking intelligent input/output ("I/O") controller employing a tightly coupled, dual modular redundant processor system, a direct memory access module and a processor support module. More particularly, the present invention relates to an I/O controller employing a pair of processors operated in lockstep and providing error protected data and address buses and dual railed, true-complement control signals that are checked by self-checking checkers in the form of morphic reduction circuits. The present invention is adapted to provide a high degree of data integrity by detecting, locating and isolating internal faults with respect to both time and geography.
2. Brief Description of the Prior Art
Commercially available, off-the-shelf microprocessors do not protect their address, data and control buses from internal faults. Consequently, such processors by themselves are inadequate for applications where integrity of data and fault tolerance are essential, such as in on-line data processing applications where large volumes of data must be handled at high transaction rates without interruption or contamination of the data within the system in the event a system fault produces an error. Some prior art systems provide error protection for address buses and data buses, but none provide such protection for control buses or lines. Without protection for these control signals certain kinds of failures cannot be detected quickly, permitting errors to propagate through the system and making fault isolation more difficult. Error propagation can lead to corruption of data, which is unacceptable in many applications. Therefore, there was needed in the art a system that could protect against errors in address, data and control signals.
Accordingly, it is a principal object of the present invention to detect, locate and isolate all single point faults and certain classes of multiple point faults, on the address, data and control buses of a dual modular redundant processor system.
It is a further object of the present invention to protect the address bus, data bus and control bus from single-point faults, either static or transient.
It is a further object of the present invention to detect such faults on a bus cycle basis.
It is a further object of the present invention to report any detected faults either on the same bus cycle during which they are detected or on the next cycle.
It is a further object of the present invention to detect, locate, isolate and report internal faults before they can propagate, either in time or geography, thereby rendering fault determination and correction substantially easier and more reliable.
It is a further object of the present invention to operate a redundant pair of commercially available microprocessors in lockstep to provide an internal system bus protected against address, data and control errors and thus ensure a high degree of data integrity.